International Journal of Network Security & Its Applications (IJNSA) - ERA, WJCI Indexed
ISSN: 0974 - 9330 (Online); 0975 - 2307 (Print)
Webpage URL: https://airccse.org/journal/ijnsa.html
Low Area FPGA Implementation of DROM-CSLA-QTL Architecture for Cryptographic Applications
Shailaja A1 and Krishnamurthy G N2, 1VTU-RRC, India and 2BNM Institute of Technology, India
Abstract
Nowadays, several techniques are implemented for the cryptosystems to provide security in communication systems. The major issues detected in conventional methods are the weakness against different attack, unacceptable data expansion, and slow performance speed. In this paper, a method Dual-port Read Only Memory-Carry Select Adder-Quantitative Trait Loci (DROM-CSLA-QTL) is introduced, which utilizes lower area than the existing method. The proposed system is implemented using DROM-CSLA, which occupies less area. The DROM-CLSA-QTL algorithm is implemented using tools such as MATLAB and Model Sim. Further for FPGA implementation, Virtex 4, Virtex 5 and Virtex 6 devices are used to determine the number of Lookup Tables (LUTs), slices, flip-flops, area and frequency. Mean, Variance and Covariance are evaluated in the MATLAB.
Keywords
Cryptosystem, Dual-Port read-only memory, Carry select adder, Quantitative trait loci, and MATLAB
Original Source URL: https://aircconline.com/ijnsa/V10N3/10318ijnsa03.pdf
Volume URL: https://airccse.org/journal/jnsa18_current.html
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