DESIGN OF REVERSIBLE MULTIPLIERS FOR LINEAR FILTERING APPLICATIONS IN DSP

Rakshith Saligram1  and Rakshith T.R2

1Department of Electronics and Communication, B.M.S College of Engineering, Bangalore, India

2Department of Telecommunication, R. V College of Engineering, Bangalore, India

ABSTRACT

Multipliers in DSP computations are crucial. Thus modern DSP systems need to develop low power multipliers to reduce the power dissipation. One of the efficient ways to reduce power dissipation is by the use of bypassing technique. If a bit in the multiplier and/or multiplicand is zero the whole array of row and/or diagonal will be bypassed and hence the name bypass multipliers. This paper presents the column Bypass multiplier and 2-D bypass multiplier using reversible logic; Reversible logic is a more prominent technology, having its applications in Low Power CMOS and quantum computations. The switching activity of any component in the bypass multiplier depends only on the input bit coefficients. These multipliers find application in linear filtering FFT computational units, particularly during zero padding where there will be umpteen numbers of zeros. A bypass multiplier reduces the number of switching activities as well as the power consumption, above which reversible logic design acts to further almost nullify the dissipations.

KEYWORDS

Reversible logic, Low power Multipliers, Column Bypass multiplier, 2-D Bypass Multiplier ,Reduced Switching Activity, Fast Fourier Transform, Zero Padding. 

Original Source Link : http://aircconline.com/vlsics/V3N6/3612vlsics06.pdf

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