LOW AREA FPGA IMPLEMENTATION OF DROMCSLA-QTL ARCHITECTURE FOR CRYPTOGRAPHIC APPLICATIONS
Shailaja A1 and Dr Krishnamurthy G N2
1Research Scholar, V T U RRC, Belagavi, Karnataka, India
2Principal, B N M Institute of Technology, Bangalore, Karnataka, India
ABSTRACT
Nowadays, several techniques are implemented for the cryptosystems to provide security in communication systems. The major issues detected in conventional methods are the weakness against different attack, unacceptable data expansion, and slow performance speed. In this paper, a method Dual-port Read Only Memory-Carry Select Adder-Quantitative Trait Loci (DROM-CSLA-QTL) is introduced, which utilizes lower area than the existing method. The proposed system is implemented using DROM-CSLA, which occupies less area. The DROM-CLSA-QTL algorithm is implemented using tools such as MATLAB and Model Sim. Further for FPGA implementation, Virtex 4, Virtex 5 and Virtex 6 devices are used to determine the number of Lookup Tables (LUTs), slices, flip-flops, area and frequency. Mean, Variance and Covariance are evaluated in the MATLAB.
KEYWORDS
Cryptosystem, Dual-Port read-only memory, Carry select adder, Quantitative trait loci, and MATLAB.
Original Source Link : http://aircconline.com/ijnsa/V10N3/10318ijnsa03.pdf
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